Single crystal photovoltaic devices, especially silicon photovoltaic devices have been utilized for some time as sources of electrical power because they are inherently non-polluting, silent, and consume no expendable natural resources in their operation. However, the utility of such devices is limited by problems associated with the manufacture thereof. More particularly, single crystal materials (1) are difficult to produce in sizes substantially larger than several inches in diameter, (2) are thicker and heavier than their thin film counterparts; and (3) are expensive and time consuming to fabricate.
Recently, considerable efforts have been made to develop processes for depositing amorphous semiconductor films, each of which can encompass relatively large areas, and which can be doped to form p-type and n-type materials for the production of p-i-n type devices substantially equivalent to those produced by their crystalline counterparts. It is to be noted that the term "amorphous" as used herein, includes all materials or alloys which have long range disorder, although they may have short or intermediate range order or even contain, at times, crystalline inclusions.
It is now possible to prepare by glow discharge or other vapor deposition techniques, thin film amorphous silicon or germanium based alloys in large areas, said alloys possessing acceptable concentrations of localized states in the energy gaps thereof and high quality electronic properties. Suitable techniques are fully described in U.S. Pat. No. 4,226,898, entitled "Amorphous Semiconductor Equivalent to Crystalline Semiconductors," which issued to Stanford R. Ovshinsky and Arun Madan on Oct. 7, 1980 and in U.S. Pat. No. 4,217,374, under the same title, which issued on Aug. 12, 1980, to Stanford R. Ovshinky and Masatsugu Izu, and in U.S. Pat. No. 4,504,518 of Stanford R. Ovshinsky, David D. Allred, Lee Walter and Stephen J. Hudgens entitled "Method of Making Amorphous Semiconductor Alloys and Devices Using Microwave Energy," which issued on Mar. 12, 1985, and in U.S. Pat. No. 4,517,223 under the same title which issued on May 14, 1985 to Stanford R. Ovshinsky, David D. Allred, Lee Walter and Steven J. Hudgens, which patents are assigned to the assignees of the instant invention, the disclosures of which are incorporated herein by reference. As disclosed in these patents, it is believed that fluorine introduced into the amorphous semiconductor operates to substantially reduce the density of the localized states therein and facilitates the addition of other alloying materials.
The concept of utilizing multiple cells, to enhance photovoltaic device efficiency, was disclosed at least as early as 1955 by E. D. Jackson in U.S. Pat. No. 2,949,498, issued Aug. 16, 1960. The multiple cell structures therein disclosed utilized p-n junction crystalline semiconductor devices. Essentially, the concept is directed to utilizing different band gap devices to more efficiently collect various portions of the solar spectrum and to increase open circuit voltage (Voc.). The tandem cell device has two or more cells with the light directed serially through each cell, with a large band gap material followed by a smaller band gap material to absorb the light passed through the first cell or layer. By substantially matching the generated currents from each cell, the overall open circuit voltage is the sum of the open circuit voltage of each cell while the short circuit current remains substantially constant. It should be noted that Jackson employed crystalline semiconductor materials for the fabrication of the stacked cell device; however, it is virtually impossible to match lattice constants of differing crystalline materials. Therefore, it is not possible to fabricate such crystalline tandem structures in a commercially feasible manner. As the assignee of the instant invention has shown however, such tandem structures are not only possible, but can be economically fabricated in large areas by employing amorphous materials.
It is of obvious commercial importance to be able to mass produce photovoltaic devices such as solar cells. However, with crystalline cells, mass production was limited to batch processing techniques by the inherent growth requirements of the crystals. Unlike crystalline silicon, amorphous silicon and germanium alloys can be deposited in multiple layers over large area substrates to form solar cells in a high volume, continuous processing system. Such continuous processing systems are disclosed in the following U.S. Pat. Nos. 4,400,409, for "A Method of Making P-Doped Silicon Films And Devices Made Therefrom"; 4,410,588, for "Continuous Amorphous Solar Cell Deposition And Isolation System And Method"; 4,542,711, for "Continuous Systems For Depositing Amorphous Semiconductor Material"; 4,492,181 for "Method And Apparatus For Continuously Producing Tandem Amorphous Photovoltaic Cells"; and 4,485,125 for "Method And Apparatus For Continuously Producing Tandem Amorphous Photovoltaic Cells". As disclosed in these patents, the disclosures of which are incorporated herein by reference, a substrate may be continuously advanced through a succession of deposition chambers, wherein each chamber is dedicated to the deposition of a specific semiconductor material. In making a solar cell of n-i-p type configuration, the first chamber is dedicated for depositing a n-type amorphous silicon alloy, the second chamber is dedicated for depositing an intrinsic amorphous silicon alloy, and the third chamber is dedicated for depositing a p-type amorphous silicon alloy.
Since each deposited semiconductor alloy, and especially the intrinsic semiconductor alloy, must be of high purity; (1) the deposition environment in the intrinsic deposition chamber is isolated, by specially designed gas gates, from the doping constituents within the other chambers to prevent the diffusion of doping constituents into the intrinsic chamber; (2) the substrate is carefully cleansed prior to initiation of the deposition process to remove contaminants; (3) all of the chambers which combine to form the deposition apparatus are sealed and leak checked to prevent the influx of environmental contaminants; (4) the deposition apparatus is pumped down and flushed with a sweep gas to remove contaminants from the interior walls thereof; and (5) only the purest reaction gases are employed to form the deposited semiconductor materials. In other words, every possible precaution is taken to insure that the sanctity of the vacuum envelope formed by the various chambers of the deposition apparatus remains uncontaminated by impurities, regardless of origin.
The layers of semiconductor material thus deposited in the vacuum envelope of the deposition apparatus may be utilized to form a photovoltaic device including one or more p-i-n cells, one or more n-i-p cells, a Schottky barrier, as well as photodiodes, phototransistors, or the like. Additionally, by making multiple passes through the succession of deposition chambers, or by providing an additional array of deposition chambers, multiple stacked cells of various configurations may be obtained.
As should be apparent from the foregoing discussion, thin film amorphous semiconductor alloy materials offer several distinct advantages over crystalline materials, insofar as they can be easily and economically fabricated by the newly developed mass production processes. However, in the fabrication of semiconductor material by the aforementioned processes, the presence of current-shunting defects has been noted. These defects have (1) seriously impaired the performance of the photovoltaic devices fabricated therefrom and (2) detrimentally affected production yield. These process-related defects are thought to either (1) be present in the morphology of the substrate electrode, or (2) develop during the deposition of the semiconductor layers. It is to the end of eliminating, or at least substantially reducing the effects of these current-shunting defects to which the instant invention is directed.
The most important of these defects may be characterized as "shunts", "short-circuits", defect regions, or low resistance current paths. Before the suspected causes of these defects are explained, it will be helpful to note the thicknesses of the deposited layer of semiconductor alloy material. In a typical n-i-p type photovoltaic device, the "p" layer may be only on the order of 250 angstroms thick, the "i" layer may be only on the order of 3,500 angstroms thick, and a typical "n" layer may be only on the order of 250 angstroms thick, thereby providing a total semiconductor body thickness of only about 4,000 angstroms. It should therefore be appreciated that irregularities, however small, will not be readily covered by the deposited semiconductor layers.
Shunt defects are present when one or more low resistance current paths develop between the electrodes of the photovoltaic device. Under operating conditions, a photovoltaic device in which a shunt defect has developed, exhibits either (1) a low power output, since electrical current collected at the electrodes flows through the defect region (the path of least resistance) in preference to an external load, or (2) complete failure where sufficient current is shunted through the defect region to "burn out" the device.
While shunt-type defects always deleteriously affect the performance of photovoltaic devices, their effect is greatest when the devices in which they are incorporated are operated under relatively low illumination such as room light, vis-a-vis, high intensity illumination such as an AM-1 solar spectrum. Under room light illumination, the load resistance of the cell (i.e., the resistance under which the cell is designed to operate most efficiently) is comparable to the shunt resistance (i.e., the internal resistance imposed by the defect region), whereas under AM-1 illumination, the load resistance is much lower by comparison. This occurs because, in a photovoltaic device, photogenerated current increases linearly with increasing illumination, while the resulting voltage increases exponentially. In other words, voltage attains a relatively high value under low illumination, the value increasing only slightly as the intensity of the illumination is increased. Therefore, under low illumination the relatively high voltage potential present preferentially drives the relatively small number of photogenerated current carriers through the path of least resistance, i.e., the low resistance defect regions. In contrast thereto, under high illumination, a large number of current carriers are present and are driven by a potential of about the same magnitude as the potential which exists under low illumination. This larger number of current carriers compete for a limited number of least resistance paths (through the defect regions). The result is that at high intensity illumination, while more power may be lost to the defect region, the power lost represents a smaller percentage of the total power produced than at low intensity illumination.
Defects or defect regions, the terms being interchangeably used herein, are not limited to "overt" or "patent" short circuit current paths. In some cases, the adverse effects of a defect are latent and do not immediately manifest themselves. Latent defects can give rise to what will be referred to hereinafter as an "operational mode failure", wherein a photovoltaic device, initially exhibiting satisfactory electrical performance, suddenly fails. The failures will be referred to in this application as operational mode failures regardless of whether the device was previously connected to a load for the generation of power, it only being necessary that the device was, at some time, subjected to illumination, thereby initiating the generation of carriers. This type of failure will be discussed in further detail hereinbelow. It is believed the shunt defects, both latent and patent, arise from one or more irregularities in the (1) morphology of the substrate material, or (2) in the growth of the semiconductor layers.
The first, and perhaps most important, source of the defects, i.e., the aforementioned morphological irregularities in the deposition surface of the substrate material will now be discussed. Even though the highest quality stainless steel is employed to serve as the substrate or base electrode upon which the semiconductor layers are successively deposited, it has been calculated that from 10,000 to 100,000 irregularities per square centimeter are present on the deposition surface thereof. Such irregularities take the form of projections, craters, or other deviations from a smooth finish and may be under a micron in (1) depth below the surface, (2) height above the surface, or (3) diameter. Regardless of their configuration or size, the defects may establish a low resistance current path through the semiconductor body, thereby effectively short-circuiting the two electrodes. This may occur in numerous ways. For instance, a spike projecting from the surface of the substrate electrode may be of too great a height to be covered by the subsequent deposition of semiconductor layers, and therefore, be in direct electrical contact with the other electrode when that electrode is deposited atop the semiconductor layers. Likewise, a crater formed in the surface of the substrate electrode may be of too small a size to be filled by the subsequent deposition of semiconductor layers and therefore, be in relatively close proximity to the other electrode, when that electrode is deposited atop the semiconductor layers. In such an instance; (1) electrical current may bridge the gap which exists between the electrodes, or (2) during actual use (the photoinduced generation of electrical current) of the photovoltaic device, the material of one of the electrodes may, under the influence of the electrical field, migrate toward and contact the other of the electrodes, and thereby pass electrical current therebetween. It is also possible that in some cases the semiconductor layers deposited onto the substrate include regions of irregular composition which can provide low resistance paths for the flow of electrical current between the electrodes of the photovoltaic device.
Further, despite all the previously described efforts to maintain the vacuum envelope free of external contaminants; dust or other particulate matter, which somehow either (1) invades the vacuum envelope during the deposition of the semiconductor material, or (2) forms as a by-product of the deposition process, may be deposited over the substrate electrode along with the semiconductor material. The contaminants interfere with the uniform deposition of the semiconductor layers and may establish the low resistance current paths therethrough.
Additionally, it is suspected that in some cases, the semiconductor material may form micro-craters or micro-projections during the deposition thereof, even absent the presence of contaminants or pollutants from external sources. Such morphological deviation from a perfectly smooth and even surface means that the substrate is covered by semiconductor alloy material either (1) in an "ultra thin layer" (consider again that the total thickness of all semiconductor layers is only on the order of 4,000 angstroms and any reduction in coverage is indeed an ultra thin layer) or (2) not at all. Obviously, when the upper electrode material is deposited across the entire surface of the semiconductor body, the defect regions cause the low resistance current path to develop, and electrical current is shunted therethrough. In still other cases involving defect regions, the presence of such defect regions are only detectable due to their deleterious effect upon the electrical and photoelectric properties of the resultant photovoltaic device. Finally, note the defects described hereinabove may not be sufficiently severe to divert all electrical current through the low resistance path. However, the diversion or shunting of any current therethrough represents a loss in operational efficiency of the photovoltaic device and should therefore be eliminated. Moreover, the shunting of even small amounts of current through each of thousands of defect regions may combine to cause major losses in efficiency. Based upon the foregoing, it should be apparent that a reduction in current flow through these defects and defect regions is critical to the fabrication of high-yield, high efficiency, large area thin film photovoltaic devices.
Several approaches dealing with this problem have been implemented by Applicants and their colleagues. As described in U.S. Pat. No. 4,451,970, of Masatsugu Izu and Vincent Cannella, entitled "System and Method For Eliminating Short Circuit Current Paths In Photovoltaic Devices," said patent assigned to the assignee of the instant application, the shunting of current through defect regions is treated by substantially eliminating the defect regions as an operative area of the semiconductor device. This is accomplished in an electrolytic process where electrode material is removed from the periphery of the defect site, effectively isolating the defect regions and preventing the flow of electrical current through the defect region. However, the process described in the '970 patent is current dependent, i.e., the greater the current flowing through a particular area of the device, such as a defect region, the greater the amount of electrode material (in the preferred embodiment indium tin oxide) removed. Consequently, said short circuit eliminating process performs admirably in removing the electrode material from the periphery of a large defect, and thereby preventing all current flow therethrough. However, it is not as successful in eliminating the flow of current between the electrodes in the thousands of defect regions which are relatively small. And as previously mentioned, since a great many relatively small current shunting paths taken in toto, divert a substantial amount of current from its desired path of travel, the low resistance current paths created by such small defect regions must also be eliminated or at least substantially reduced. Further, the electrolytic process described in the '970 Patent neither detects nor helps in preventing the formation of current-shunting paths in the case of operational mode failures.
In U.S. Pat. No. 4,419,530 to Prem Nath, entitled "Improved Solar Cell And Method For Producing Same", and assigned to the assignee of the instant patent application, there is described a method for electrically isolating small area segments of an amorphous, thin film, large area photovoltaic device. This isolation of defects is accomplished by (1) dividing the large area device into a plurality of small area segments, (2) testing the small area segments for electrical operability, and (3) electrically connecting only those small area segments exhibiting a predetermined level of electrical operability, whereby a large area photovoltaic device comprising only electrically operative small area segments is formed.
While the method of Nath is effective in reducing or eliminating the effect of defects, it is not completely satisfactory for several reasons. The step of dividing the semiconductor body of the solar cell into electrically isolated portions requires several production steps and also reduces the total area of the solar cell that is available for producing electrical energy. Further, the method can be time and cost intensive since the electrical output of each isolated portion must be tested and separate electrical connections must be made to provide electrical contact to each small area segment. Also, since an entire segment is effectively eliminated from the final cell if it manifests a defect, proportional losses of efficiency are greater than they would be if only the precise area of the particular defect were eliminated. In addition, it is possible that defects (shorts) in a solar cell can develop after the cell has been in use, and the concept of dividing the body of the large area cell does not correct this type of defect.
Further, both of the foregoing patent applications relate to "after market" techniques which are applicable to (1) isolate only gross defect-containing regions, and (2) prevent any and all current flow through those defect containing regions. Accordingly, a need still exists for a photovoltaic device which substantially eliminates the deleterious effects of shunts and other defects, both large and small, whatever their origin, without operatively removing large portions of the active semiconductor body while maintaining an acceptable level of current flow across the entire surface of the device.
One such method and device is disclosed in commonly assigned U.S. Pat. No. 4,590,327 to Nath, et al, issued May 20, 1986 and entitled "Photovoltaic Device And Method", assigned to the assignee of the subject application and the disclosure which is incorporated herein by reference. Disclosed therein are several configurations of current collecting bus grid structures for photovoltaic devices, said structures specifically designed to minimize the effects of shorts, shunts, and other defects upon the performance of the devices.
A differently configured photovoltaic device and method for eliminating the problems of shorts and shunts is disclosed in U.S. patent application Ser. No. 699,523 of Nath, et al, filed Feb. 8, 1985 and also entitled "Photovoltaic Device And Method", also assigned to the assignee of the subject application and the disclosure of which is incorporated herein by reference. That application concerns a photovoltaic device having the current collecting bus grid structure disposed beneath the upper, transparent conductive electrode thereof. As disclosed, the bus grid structure may optionally have a layer of insulating material disposed directly therebeneath to prevent direct electrical communication with short circuit defects in the body of semiconductor alloy material. Disposing the bus grid structure in such a manner will, as discussed in said application, prevent many of the problems associated with short circuit defects. However, new problems arise in the fabrication of such photovoltaic devices when the bus grid structure is formed as a relatively thick member because there may be instances in which the upper transparent conductive electrode of the photovoltaic device is not thick enough to fully cover a bus grid structure of relatively large thickness (for example greater than 1 micron). When thick bus grid structures are employed, breaks may occur in the transparent conductive oxide layer, which breaks could prevent the efficient communication of electrical current to the bus grid structure. In some cases this problem can be eliminated by making the bus grid structure thinner, as for example when electroplated metal is utilized for the fabrication thereof; however, in many instances it may be desirable or necessary to employ materials such as conductive inks or pastes for the fabrication of the bus grid structure, which materials cannot be readily applied in thin layers. Furthermore, alignment of the bus grid structure with the underlying insulative material necessitates a precise registration thereof, if proper operation of the invention is to be attained.
Another approach to the elimination of short circuit current paths is detailed in U.S. patent application Ser. No. 699,524, of Nath, et al, filed Feb. 8, 1985 and also entitled "Photovoltaic Device and Method", also assigned to the assignee of the subject application and the disclosure of which is incorporated herein by reference. As detailed therein, a photovoltaic device having an increased tolerence to defects is provided by disposing a layer of current flow restricting material beneath at least portions of the bus grid structure in order to prevent the flow of large amounts of current, as would be routinely encountered at a defect site, through the photovoltaic body and to the bus grid. While the invention performs its function of limiting current flow through defective regions of a photovoltaic cell, implementation of the invention is made difficult, particularly in a high-volume production process by the necessity of maintaining vertical alignment of the bus grid structure with the underlying current flow restricting material. Since the bus grid structure includes many finely detailed features, and since the photovoltaic cell is of relatively large area, particular care and control must be exercised to assume this proper registration.
Accordingly, there exists need for a defect tolerant photovoltaic device manufactured by a process which does not require precise alignment steps, i.e., by a process which is particularly suitable for mass production. Disclosed herein are configurations of photovoltaic devices which exhibit a high degree of operational tolerance to the presence of defects therein and which may be fabricated on a mass production basis without requiring precision alignment steps.